CMOS Low Noise Amplifier Design Optimization Techniques

This paper reviews and analyzes four reported low noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching (CNM), simultaneous noise and input matching (SNIM), powerconstrained noise optimization (PCNO), and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this work provides clear understanding of the design principles, the fundamental limitations, and the advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low power foldedcascode LNA is implemented based on 0.25 μm CMOS technology for 900 MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and IIP3 of –4 dBm while dissipating 1.6 mA from 1.25 V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.